Siemens and TSMC have expanded their collaboration on AI-powered chip design. The companies have enabled an AI agent to automate design rule check fixing. Design rule checks are automated checks that catch chip-layout errors.

The agent works across digital and custom integrated circuit design flows. It is powered by Siemens' Calibre software and integrated with Aprisa and Solido tools. The goal is to reduce manual effort and speed up time-to-tapeout, the chip's design-to-production timeline.

The announcement came at TSMC's 2026 North America OIP Ecosystem Forum on September 23. Ankur Gupta, a Siemens executive vice president, said the collaboration helps customers innovate at the industry's most advanced process nodes. Cadence and Synopsys also showed agentic AI tools at the event.

Siemens said it uses Nvidia AI products to improve its EDA systems' reasoning. What matters next: foundry-enabled agentic workflows could cut design cycles for advanced chips. Faster cycles would help chipmakers manage rising design complexity.